1. Field of the Invention
The invention relates to a method of producing multi-zone semiconductor devices and somewhat more particularly to a method of producing such semiconductor devices wherein two different protective layers are used.
2. Prior Art
German Auslegeschrift 1,589,886 (which corresponds to U.S. Pat. No. 3,791,883), suggests that semiconductor devices may be produced by coating first areas of a semiconductor surface with a Si.sub.3 N.sub.4 layer and coating second areas of such semiconductor surface with SiO.sub.2 layer. Windows are then provided in at least one of the two insulating layers by photo-lacquer etching techniques to uncover select areas of the semiconductor surface and different dopants are then diffused via increased temperature into, for example, a silicon surface, so as to provide a well defined pn-junction.
Frequently, in the foregoing procedure it is necessary to insure that after the production of zones of different conductivity type by a diffusion process using SiO.sub.2 diffusion mask, the SiO.sub.2 layer which functions simultaneously as a protective layer and as a passivation layer for the pn-junction, is protected from lateral migration of Na-ions typically present in a metal contact applied to such semiconductor devices. In order to accomplish, a Si.sub.3 N.sub.4 layer is uniformly deposited on the entire surface of the semiconductor crystal and windows or openings are provided in the Si.sub.3 N.sub.4 layer down to the semiconductor crystal (generally silicon) surface. These windows are typically filled with a metal contact and they are produced in such a manner that a narrow ring of silicon surface between the SiO.sub.2 passivation layer and the metal contact are directly covered by the Si.sub.3 N.sub.4 layer.
Frequently, with this type of procedure, it is desirable to produce two or more zones in a semiconductor device, each of which exhibits different conductivity type and are of a select size and geometry on the surface of, for example, a silicon crystal. This applies, for example, to the production of an emitter zone and a base contact zone in register with a base zone during the manufacture of planar transistors. However, when doping by the so-called ion implantation technique (where ions of select dopant atoms are, as it were, "shot" into the silicon crystal and any crystal faults or the like caused thereby are eliminated or healed by subsequent heat tempering), it is also advantageous to combine a Si.sub.3 N.sub.4 layer and a SiO.sub.2 layer on the surface of a silicon crystal in the manner suggested by the aforesaid prior art patent. It is then possible to produce level or plane doping fronts or profiles as will be explained in detail hereinafter.